Various types of memory are used with integrated circuits (“ICs”). Volatile memory is a type of memory that loses its stored information when power is removed from the memory circuit. Random access memory (“RAM”) is an example of volatile memory. A RAM cell can be easily reprogrammed to a desired logic state, and is often implemented in complementary metal-oxide-semiconductor (CMOS) logic. Non-volatile memory is a type of memory that preserves its stored information even if power is removed. Read-only memory (“ROM”) is an example of non-volatile memory.
Programmable read-only memory (“PROM”) is a type of memory that is configured to a desired state. A programming signal is applied to a PROM memory cell to change the cell from a first condition (i.e., first logic state) to a second condition (i.e., a second logic state). Programmable non-volatile memory is desirable in various integrated circuits including programmable logic devices (“PLDs”), such as field-programmable gate arrays (“FPGAs”) and complex programmable logic devices (“CPLDs”). Some types of programmable non-volatile memory, such as anti-fuse based memory, can only be programmed once. Another type of programmable non-volatile memory, commonly called can be electronically programmed and erased several times. Examples of this type of non-volatile memory are commonly referred to as electronically erasable programmable read-only memory (“EEPROM”) or, if used in a CMOS IC, “CMOS NV-memory”.
Conventional CMOS NV-memory cells use floating conductive structures, such as floating poly-silicon (“poly”) gate structures, to store charge. The stored charge creates an electrical potential that affects the conductivity of an underlying channel region of a field-effect transistor (“FET”). It is generally desirable that floating gates be easily programmable using typical voltages of the CMOS IC, and also desirable that the floating gates store charge for a long period of time so that the data value programmed into an NV memory cell remains valid. It is similarly desirable that one type of data value (e.g., a logical “1”) be easily distinguished from a second type of data value (e.g., a logical “0”). However, compromises must be made to balance the various attributes desired in CMOS NV-memory.
On approach uses relatively thick dielectric (gate oxide) between the floating gate and charge source (e.g., channel region). The thick oxide provides good charge retention, but makes programming difficult and de-couples the floating gate from the channel region during VERIFY or READ operations. In other words, greater charge must be transferred to the floating gate to get the same change in threshold voltage VT that would be obtained by a thinner gate oxide. Unfortunately, thinner oxides leak charge off the floating gate, which degrades the effectiveness of the memory cell, and will eventually lead to loss of the data value stored in the memory cell. Other approaches periodically check the value of the memory cell to insure it is above an operating margin, and refresh the memory cell if it has degraded below the operating margin. However, such an approach uses additional resources for the comparison file and refresh operation.
It is desirable to provide a CMOS non-volatile memory cell that avoids the problems of the prior art.